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Day28 Log

Test 1 - I2C IRQ Mode

mode=irq
sensor_bus=i2c (1-0048)
cache_valid=1
last_source=irq
irq_enable=1
polling_enable=0
irq_event_count=3
irq_update_count=3
irq_skip_count=0
poll_event_count=0

Result

  • IRQ triggered successfully
  • update executed on every event
  • no skip
  • polling disabled

Test 2 - SPI IRQ Mode

mode=irq
sensor_bus=spi (spi0.0)
cache_valid=1
last_source=irq
irq_enable=1
polling_enable=0
irq_event_count=6
irq_update_count=6
irq_skip_count=0
poll_event_count=0

Result

  • SPI IRQ path fully functional
  • consistent update behavior with I2C
  • abstraction layer verified

Observations

  • irq_event_count == irq_update_count
  • no dropped events
  • last_source=irq confirms path
  • SPI and I2C share identical core behavior

Conclusion

  • Dual-bus IRQ model works correctly
  • Core abstraction is preserved
  • System is stable under IRQ mode