UART / TTY Subsystem Notes

1. TTY Architecture

TX Path

write()
  → tty core
  → line discipline
  → serial driver
  → UART hardware

RX Path

UART RX
  → interrupt
  → flip buffer
  → line discipline
  → tty core
  → read()

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2. Key Components

TTY Core

• manages /dev/ttyXXX
• buffering
• process interaction

Line Discipline (N_TTY)

• canonical mode
• echo
• signal handling

Serial Driver (PL011)

• hardware TX/RX
• interrupt handling

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3. Canonical vs Raw Mode

Mode	Behavior
canonical	line-based input
raw	byte stream

UART communication uses raw mode.

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4. termios / stty Important Fields

Check current config:

stty -F /dev/ttyAMA2 -a

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Speed

• speed 115200 baud → UART baudrate

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Control Flags (c_cflag)

• cs8 → 8 data bits

• -parenb → no parity

• -cstopb → 1 stop bit

• cread → enable receiver

• clocal → ignore modem control signals

• -crtscts → disable hardware flow control

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Input Flags (c_iflag)

• -ixon -ixoff → disable software flow control

• -icrnl → do not translate CR to NL

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Output Flags (c_oflag)

• -opost → disable output processing

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Local Flags (c_lflag)

• -icanon → raw mode (no line buffering)

• -echo → disable echo

• -isig → disable signal handling (Ctrl+C)

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Control Characters

• VMIN
• VTIME

Example:

• min = 0
• time = 10

Meaning:

• non-blocking read
• 1 second timeout

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5. Why Python Test Works Better

Python test:

• single process
• explicit termios config
• controlled timing
• uses flush

Shell test:

• multiple processes
• implicit config
• race conditions

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6. Key Insight

TTY is not a simple char device.

driver → flip buffer → tty core → user

Instead of:

driver → copy_to_user

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7. Summary

• UART is hardware
• TTY is abstraction
• termios is control plane
• line discipline processes data
• serial driver handles hardware